
Senior Engineer, Design Verification
- Philippines
- Permanent
- Full-time
- Block / top level verification
- Composition and review of Verification Plans and tracking
- Develop successful products in a fast-paced, high growth product line
- Support test engineers, application engineers and software engineers
- Mentoring and partial coordination of P2 Engineers activities
- Metric-Driven Verification application (Regression maintenance and Coverage closure)
- Integrating AMS and DMS activities
- Master’s degree in EE with 2 years’ experience or bachelor’s degree with 7 years’ experience
- Strong fundamentals in IC design, especially digital design
- Sound analytical skills
- Understanding of digital signal processing
- Strong technical writing and communication skills
- UVM Practical knowledge
- Any regression management system
- Fluent in any of the major text editors in use (Emacs, *Vim, VSCode, Nedit, Jedit, …)
- Cadence Virtuoso environment working principles, SKILL fundamentals.
- Fluent in Matlab, System C, SystemVerilog, Lisp/Functional programming.
- Knowledge of Verilog AMS
- Knowledge of Cadence Virtuoso, Maestro, Explorer, Assembler
- Experience writing assertions in SVA or equivalent
- DSP experience from filter design to high level implementation
- Power management components (LDO, Buck, Buck-Boost, Charge Pump) working principles
- Experience with industry standard design tools including simulation, formal verification, synthesis, timing analysis, ECO, CDC and LINT; touch typing will be appreciated.