- Develop comprehensive verification plans, clear metrics and continuously measure progress against the plan throughout the project
- Verify design blocks, sub systems and full chip using assertion-based verification, formal verification, directed tests and randomized tests
- Understand the specifications, use cases and develop System Verilog and ‘C’ based testbenches in UVM environment
- Design and develop testbench components such as Universal Verification Components, BFMs and verification tools
- Define and design verification regression environment
- Perform Functional coverage, RTL code coverage, assertion coverage, and gate level simulations
- Collaborate with design engineers, IP developers and SW developers to deliver high quality SoC verification on aggressive time schedules
- Develop best practices and world class methods for SoC verification
- Highly skilled in debugging and analyzing complex digital designs.
- Expert HDL and HVL Languages and methodologies (Verilog, VHDL, SystemVerilog, UVM/OVM etc.)
- Familiar with ASIC/FPGA/SoC verification process/development cycle.
- Expert in using simulation tools like Cadence IES/Xcelium, Synopsys VCS or Mentor’s Questa
- Have hands-on experience in Python, Perl or shell scripting, TCL, make.
- Strong communication, analytical and documentation skills and ability to interface with other groups/site.
- Stay up to date on industry trends and direction of verification technology development
Team Player: Works well as a member of a group
Functional Expert: Considered a thought leader on a subject
Innovative: Consistently introduces new ideas and demonstrates original thinking
Motivation : Self-Starter: Inspired to perform without outside help
Ability to Make an Impact: Inspired to perform well by the ability to contribute to the success of a project or the organization
Flexibility: Inspired to perform well when granted the ability to set your own schedule and goals
Education : Bachelors
Experience : 5 years: Design Verification